This invention relates to a memory device such as a dynamic random access memory (DRAM) of high density, and more particularly to a flash writing circuit for testing such DRAMs.
As the DRAM becomes more and more highly integrated, precise processes for the fabrication of many layers and patterns of the devices are required, and the fault rate of the DRAM is determined by the amount of dust contaminants. Particularly, as the integration degree of the DRAMs increases, the fault rate is also increased so that, recently, DRAM-testing circuits are built within the memory device to perform an internal testing of the devices. Even if the testing of the DRAM is internally performed, the DRAM-testing time becomes longer in case of higher integration.
That is, in the conventional testing technique, the DRAM-test is carried out by a bit unit (x4, x8, x16) using test signals. The time required for testing increases according to the ratio of the integration density/xbit. Accordingly, the more integration density increases, the more test time increases since the writing and reading of the data are performed by a xbit unit through input/output lines and the read out data are analyzed to check for errors.
To reduce testing time, there has been developed a flash DRAM testing method which can write at one time the test data into each of the memory cells connected to a selected word line by writing and comparing directly the data on the bit lines, such writing being done without the use of the input/output (I/O) lines. In another flash writing method, the writing is made through the I/O lines. However, these methods can't write all the same data (1 or 0) into the memory cells connected to the selected word line according to the position of the bit lines and memory cells since the bit lines B/L and B/L are located in a constant sequence, that is, B/L, B/L, B/L, B/L, B/L, B/L, B/L, B/L, . . .